Recent developments in telecommunications technology have led to service-integrated communications transmission and switching systems for narrow band and broadband communication services which provide light waveguides as the transmission medium in the region of the subscriber lines by way of which both the narrow band communications services such as, in particular, 64 kbit/s digital telephony, and broadband communications services such as, in particular, 140 Mbit/s picture telephony, are conducted, whereby, however, dedicated narrow band signal switching equipment and broadband signal switching equipment are provided in the exchanges preferably comprising shared control devices, such as in the U.S. Pat. No. 3980 831 (German Pat. No. 24 21 002), fully incorporated herein by this reference.
In conjuction with the broadband signal time-division multiplex switching equipment whose crosspoints are utilized in time-division multiplex for a respective plurality of connections, it is known to connect, respectively, two lines with the assistance of a gate circuit which is switched on and off by a crosspoint-associated memory cell constructed as a bistable D flip-flop, whereby this cross-point associated memory cell, whose clock input is supplied with a corresponding clock signal, is driven in only one coordinate direction, namely at its D input. In this connection one may take reference to Pfannschmidt: "Arbeitsgeschwindigkeitsgrenzen von Koppelentzwerken fuer Breitband-Digitalsignale", Diss., Braunschweig, 1978, FIG. 6.7 and FIG. 6.4. In view of a time-division multiplex factor of about 4-8, which can be achieved in view of a bit rate of 140 Mbits/s and in view of the involved circuit technology thereby required, however, exclusive space-division switching facilities are presently preferred for switching broadband signals, the connections by way of the individual crosspoints being separted from one another therein only on spatial basis.
An exclusive broadband signal space-division switching matrix network can be constructed as a crosspoint matrix in complementary-metal-ooxide-semiconductor (CMOS) technology, provided with input amplifiers and output amplifiers, in whose crosspoints the switching elements are respectively controlled by a decoder-controlled, crosspoint-associated holding memory cell, whereby the switch elements are respectively constructed as a CMOS transfer gate (CMOS transmission gate: ISS'84 Conference Papers 23 Cl, FIG. 9); the crosspoint-associated holding memory cells of an exclusive spaced-division switching matrix can be driven in two coordinates proceeding from a row decoder and from a column decoder, being respectively driven via a row-associated or, respectively, column-associated select line (Pfannschmidt, Op. Cit, FIG. 6.4). Output amplifiers provided in a switching matrix can be activated dependent on the activation of at least one crosspoint of the appertaining matrix line, as in the French Pat. No. 2,365,263, FIG. 5, fully incorporated herein by this reference.
It is likewise known in general form, from Electronics, Dec. 15, 1983, pp. 88-89, to provide digital crosspoints in the form of tristate inverters in a broadband crosspoint matrix, the specific realization of these tristate inverters being thereby unresolved but at least requiring a plurality of transistors.
A particularly low transistor expense in the specific realization of the individual crosspoints is comprised by a broadband signal space-division switching equipment, such as disclosed in the U.S. Ser. No. 013,069 (German No. 36 04 605.1), also fully incorporated herein by this reference, comprising a crosspoint matrix in field effect transistor (FET) technology whose switching elements are respectively controlled by a decorder-controlled, cross-point-associated memory cell in which the switch elements are respectively formed by a single n-channel transistor charged at its gate electrode with a switching potential which exceeds the upper limit value of a signal to be through-connected by more than the transistor pinch-off voltage or, respectively, is charged with an inhibit potential falling below the level derived by increasing the lower limit value of a signal to be through-connected by the transistor pinch-off voltage. Switch elements provided in a crosspoint matrix and respectively controlled in a simple manner by way of a crosspoint-associated holding memory cell can therefore be realized with minimum transistor expense, without inverters and without a p-channel transistor to be provided in a CMOS transfer gate which requires a larger area because of its higher specific resistance and, therefore, can be realized with a correspondingly low spaced requirement and with correspondingly low switch capacitances, this being particularly important in integration.
An additional reduction in the size of the circuit and, therefore, of the space requirement for such a crosspoint derives with a crosspoint-associated memory cell driven in two coordinate directions by two selection decoders (row decorder, column decoder), this memory cell being constructed with an n-channel transistor and two cross-coupled inverter circuits whose one's input is connected to the appertaining decoder output of the one selection decoder via the n-channel transistor which is, in turn, charged at its control electrode with the output signal of the appertaining decoder output of the other selection decoder and whose one's output leads to the control input of the appertaining switch element.
Arbitrarily, asynchronous signals having bit rates up to the order of magnitude of 170 Mbit/s and, therefore, in particular, what is referred to as a signal (for instance, a 140 Mbit/s signal) filling what is referred to as a H4-channel can be respectively through-connected between an input and an output (or, given distribution servies, a plurality of outputs) via such a proposed, broadband signal spaced-division switching equipment comprising a crosspoint matrix in FET technology having, for example, 64 inputs and 32 outputs. In the meantime, the requirement arises that not only should a respective, entire H4-channel be available to be switched but sub-channels, for example what are referred to as H3-channels, for example 34 Mbit/s signals, should also be capable of being switched. Such a sub-channel switching can be fundamentally achieved with the assistance of demultiplexers dividing the respective (H4-channels) into its (H3) sub-channels which precede the switching equipment and with the assistance of multiplexers which again combine the sub-channels to form a channel following the switching equipment, whereby the switching equipment itself respectively switches the individual sub-channels by themselves. This, however, assumes a corresponding multiplication of the inputs and outputs of the crosspoint matrix which, for example, must then comprise 256.times.128 crosspoints instead of merely 64.times.32 crosspoints in this example. The requirement for complete distribution service capability of the crosspoint matrix thereby raises the problem that each of the inputs (256 inputs in this example) of such a crosspoint matrix must be capable of being simultaneously loaded by all outputs (128 in this example) of the crosspoint matrix. This would require 256 input driver circuits per se of excessively-large size whose cross currents and dissipated power, however, would considerably complicate the feasibility of such a crosspoint matrix module.